Table of Contents

1. Overview
2. Normative references
3. Definitions, abbreviations, and acronyms
4. Preface
5. Tutorial
6. Extensions to STIL.0 Clause 6 (STIL syntax description)
7. Extensions to STIL.0 Clause 8 (STIL statement)
8. Extensions to STIL.0 Clause 14 (Signals block)
    (FlowExtended)
9. Extensions to STIL.0 Clause 15 (SignalGroups block)
    (FlowExtended)
10. Extensions to STIL.0 Clause 16 (PatternExec block)
    (FlowExtended)
11. Extensions to STIL.0 Clause 17 (PatternBurst block)
    (FlowExtended)
12. Extensions to STIL.0 Clause 18 (Timing and WaveformTable
    block) (FlowExtended)
13. Extensions to STIL.0 Clause 19 (Spec and Selector blocks)
14. Extensions to STIL.2 Clause 10 (DCLevels block)
    (FlowExtended)
15. Extensions to STIL.2 Clause 12 (DCSequence) (FlowExtended)
16. Include enhancements
17. FlowVariables
18. Device to tester interface
19. SignalMap
20. Device (FlowExtended)
21. Binning
22. SoftBinDefs
23. HardBinDefs
24. BinMap
25. Flow conceptual model
26. Flow conceptual model (FlowExtended)
27. TestBase definition (FlowExtended)
28. TestType definition (FlowExtended)
29. Test
30. FlowNode
31. FlowType definition (FlowExtended)
32. Flow
33. Actions and flow control
34. TestProgram
35. Standard definitions
Annex A (informative) - Event sequence
Annex B (informative) - Top-level block sequence
        (FlowExtended)
Annex C (informative) - Usage examples (FlowExtended)
Annex D (informative) - Switching from Flow to FlowExtended

Abstract

Specifies the description of certain test flow and binning components of an integrated circuit (IC) test program in a test-hardware-independent manner.

General Product Information

Published
Document Type	Standard
Status	Current
Publisher	Institute of Electrical & Electronics Engineers
Pages
ISBN