Table of Contents

1. Overview
2. Normative references
3. Definitions, abbreviations, acronyms, and special
    terms
4. Test access port (TAP)
5. Test logic architecture
6. Test logic controllers
7. Instruction register
8. Instructions
9. Test data registers
10. Bypass register
11. Boundary-scan register
12. Device identification register
13. Electronic chip identification (ECID) register
14. Initialization data register
15. Initialization status register
16. TMP status register
17. Reset selection register
18. Conformance and documentation requirements
Annex A (informative) - Example implementation using
        level-sensitive design techniques
Annex B (normative) - Boundary Scan Description Language
        (BSDL)
Annex C (normative) - Procedural Description Language (PDL)
Annex D (informative) - Integrated examples of BSDL and PDL
Annex E (informative) - Example iApply execution flow

Abstract

Covers a general overview of the operation of a component compatible with this standard and provides a background to the detailed discussion in later clauses.

General Product Information

Published
Document Type	Standard
Status	Current
Publisher	Institute of Electrical & Electronics Engineers
Pages
ISBN
Supersedes	IEEE 1149.1B : 1994 IEEE DRAFT 1149.1 : D2000.5