Table of Contents

1 Overview
   1.1 Scope
   1.2 Purpose
2 Definitions, acronyms, and abbreviations
   2.1 Definitions
   2.2 Acronyms and abbreviations
3 Structure of this standard
4 STIL syntax description
   4.1 Reserved words
   4.2 Reserved characters
   4.3 Reserved UserFunctions
   4.4 Signal and group name characteristics
   4.5 STIL name spaces and name resolution
5 Expressions
   5.1 Constant and variable expressions
   5.2 Expression delimiters-single quotes and parentheses
   5.3 Arithmetic expressions-integer, real, time, boolean
   5.4 Pattern data expressions
   5.5 Expression processing
   5.6 Boolean-boolean_expr
   5.7 Integers-integer_expr
   5.8 Logic expressions-logic_expr
   5.9 Real expressions-real_expr
   5.10 Addition to timing expressions-time_expr
   5.11 SignalVariables-sigvar_expr
   5.12 Formal parameters in procedures and macros
   5.13 Integer lists-integer_list
6 Statement structure and organization of STIL information
7 STIL statement
   7.1 STIL syntax
   7.2 STIL example
8 UserKeywords statement
   8.1 UserKeywords syntax
   8.2 UserKeywords example
9 Variables block
   9.1 Variables block syntax
   9.2 Variables example
   9.3 Variables scoping
   9.4 Variables synchronizing
10 Signals block
   10.1 Signals block syntax
   10.2 Signals example
   10.3 Bracketed signal notation enhancement
11 SignalGroups block
   11.1 SignalGroups syntax
   11.2 SignalGroups, WFCMap, and Variables example
   11.3 Default WFCMap attribute value
   11.4 Defining indexed signal groups
12 PatternBurst block
   12.1 PatternBurst syntax
   12.2 PatternBurst example
   12.3 Tiling and synchronization of patterns
   12.4 If and While statements
13 Timing block and WaveformTable block
   13.1 Additional domain specification
   13.2 CompareSubstitute operation-s, S
14 ScanStructures block
   14.1 ScanStructures syntax
   14.2 Scan cell naming-cell_ref, chain_ref, cell_group, chain_group
   14.3 Scoping rules for ScanStructure blocks
   14.4 Example indexed list of scan cells
   14.5 Example of ScanChainGroups and ActiveScanChain
   14.6 Scan chain segments and cell groups
15 Pattern data
   15.1 Data content read back-\C, \D, \E, \S, \U, \W
   15.2 Vector data mapping and joining-\m, \j
   15.3 Specifying event data in a pattern-\e
   15.4 Using expressions within pattern data
16 Pattern statements
   16.1 Additional Pattern syntax
   16.2 Vector data constraints-F, E
   16.3 Shift and LoopData statements
   16.4 Loop statement using an integer expression
   16.5 MergedScan function
17 Procedure and macro data substitution
   17.1 Nested procedure and macro cells
   17.2 Passing parameters to variables
   17.3 Default value of formal parameters
   17.4 Data substitution using WFCConstant and SignalVariable
18 Environment block
   18.1 Environment syntax
   18.2 MAP_STRING syntax
   18.3 NameMaps example
   18.4 Compact scan-cell mapping using InheritNameMap
19 Pragma block
   19.1 Pragma syntax
20 PatternFailReport
   20.1 PatternFailReport syntax
   20.2 PatternFailReport example
Annex A (informative) Glossary
Annex B (informative) Signal mapping using SignalVariables
Annex C (informative) Using logic expression with signals
Annex D (informative) Using boolean expressions in patterns
Annex E (informative) Variables and expressions in algorithmic
        patterns
Annex F (informative) Using AllowInterleave
Annex G (informative) Vector data mapping using \m
Annex H (informative) Vector data joining using \j
Annex I (informative) Block data collection
Annex J (informative) Using Fixed and Equivalent statements
Annex K (informative) Independent parallel patterns
Annex L (informative) Applications using new ScanStructures syntax
Annex M (informative) BreakPoints using MergedScan() function
Annex N (informative) Labels and X statements for diagnostic feedback
Annex O (informative) Use of STIL.1 for specific applications
Annex P (informative) Bibliography

Abstract

Described in this document are structures to support the definition of test patterns for sub-blocks of a design (i.e., embedded cores) such that these tests can be incorporated into a complete higher level device test.

General Product Information

Published
Document Type	Standard
Status	Current
Publisher	Institute of Electrical & Electronics Engineers
Pages
ISBN
Supersedes	IEEE DRAFT 1450.1 : D22 2005