Table of Contents

1. Introduction
1.1 Document structure
1.2 SCI overview
1.3 Interconnect topologies
1.4 Transactions
1.5 Cache coherence
1.6 Reliability, availability, and support (RAS)
2. References, glossary, and notation
2.1 References
2.2 Conformance levels
2.3 Glossary
2.4 Bit and byte ordering
2.5 Numerical values
2.6 C code
3. Logical protocols and formats
3.1 Packet formats
3.2 Send and echo packet formats
3.3 Logical packet encodings
3.4 Transaction types
3.5 Elastic buffers
3.6 Bandwidth allocation
3.7 Queue allocation
3.8 Transaction errors
3.9 Transmission errors
3.10 Address initialization
3.11 Packet encoding
3.12 SCI-specific control and status registers
4. Cache-coherence protocols
4.1 Introduction
4.2 Coherence
4.3 Minimal-set coherence protocols
4.4 Typical-set coherence protocols
4.5 Full-set coherence protocols
4.6 C-code naming conventions
4.7 Coherent read and write transactions
5. C-code structure
5.1 Node structure
5.2 A node's linc component
5.3 Other node components
6. Physical layers
6.1 Type 1 module
6.2 Type 18-DE-500 signals and power control
6.3 Type 18-DE-500 module extender cable
6.4 Type 18-DE-500 cable-link
6.5 Serial interconnection
7. Bibliography
Annex A. Ringlet initialization
Annex B. SCI design models
B.1 Fast counters
B.2 Translation-lookaside-buffer coherence
B.2.1 Virtual addressing
B.2.2 TLB-purge options
B.2.3 Interrupt-driven purges
B.2.4 Direct-register purges
B.2.5 Coherently purged TLBs
B.3 Coherent lock models
B.4 Coherence-performance models
B.4.1 Nonblocking message queues
Numerous figures
Numerous tables

Abstract

Defines an interface standard for vey high performance multiprocessor systems that supports a coherent shared-memory model scalable to systems with up to 64K nodes. Will encompass two levels of interface over distances less than 10 m: the physical layer and the logical layer.

General Product Information

Published
Document Type	Standard
Status	Current
Publisher	Institute of Electrical & Electronics Engineers
Pages
ISBN