Table of Contents

1. Introduction
2. Classification of Block-Transfer Modes
2.1 CAMAC Address Sequencing
2.2 Synchronization Source
2.3 Block-Transfer Termination
3. Block-Transfer Modes Described in IEEE Std 583
      (EUR 4100)
3.1 UCS (Stop) Mode
3.2 ACA (Address Scan) Mode
3.3 UQC (Repeat) Mode
4. Additional Block-Transfer Modes
4.1 UCW (Stop-on-Word) Mode
4.2 ULS (LAM Synchronized Stop) Mode
4.3 UDS (Direct Synchronized Stop) Mode
4.4 MCA (Multidevice Action) Mode
5. Compatibility
5.1 Block-Transfer Mode MCA
5.2 Block-Transfer Modes XCX, XLS, XDS
5.3 Block-Transfer Modes ULS, UDS, ULC, UCD, UQC
5.4 Block-Transfer Modes ULX, UDX, ULW, UDW
6. Hardware Design
6.1 Module Design - Q Response
6.2 Module Design - LAM Signal
6.3 Interface Design
7. Software Considerations
8. References
APPENDIX
A1. Other Block-Transfer Modes
A1.1 MCQ (Multiple Test) Mode
A1.2 ECA (Extended Address Scan) Mode
A1.3 UQL (Pause) Mode
TABLES
1. Block-Transfer Mode Descriptor
2. Block-Transfer Names
3. Compatibility Aspects of Stop and Stop-on-Word
      Block Transfer Termination Modes
4. Single Module, Single Address Block Transfer:
      Recommended Method for Performing UCS (Stop) Mode
      and Corresponding LAM Synchronized CAMAC Block
      Transfers
5. Recommended Method for Performing ACA (Address Scan)
      and UQC (Repeat) Mode CAMAC Block Transfers
6. Method for Performing UCW (Stop-on-Word) Mode and
      Corresponding LAM Synchronized CAMAC Block Transfers
FIGURE
1. Recommended Implementation of a Module's LAM Signal
      Which is Intended for Block-Transfer Synchronization;
      Simplified Block Diagram

Abstract

Presents recommended algorithms to encourage uniformity in design of CAMAC modules and controllers with resulting increased compatibility.

General Product Information

Published
Document Type	Standard
Status	Current
Publisher	Institute of Electrical & Electronics Engineers
Pages
ISBN