M00028997
New product
INFORMATION TECHNOLOGY - AT ATTACHMENT WITH PACKET INTERFACE - 7 - PART 1: REGISTER DELIVERED COMMAND SET, LOGICAL REGISTER SET (ATA/ATAPI-7 V1)
International Organization for Standardization
In stock
Warning: Last items in stock!
Availability date: 11/05/2021
FOREWORD<br>INTRODUCTION<br>1 Scope<br>2 Normative references<br>3 Definitions, abbreviations and conventions<br> 3.1 Definitions and abbreviations <br> 3.2 Abbreviations <br> 3.3 Conventions <br>4 General operational requirements<br> 4.1 Command delivery<br> 4.2 Register delivered data transfer command sector <br> addressing <br> 4.3 General feature set<br> 4.4 PACKET Command feature set<br> 4.5 Power Management feature set<br> 4.6 Advanced Power Management feature set<br> 4.7 Security Mode feature set<br> 4.8 SMART (self-monitoring, analysis and reporting <br> technology) feature set<br> 4.9 Host Protected Area feature set <br> 4.10 CompactFlash Association (CFA) feature set <br> 4.11 Removable Media Status Notification and Removable <br> Media feature sets<br> 4.12 Power-Up in Standby feature set<br> 4.13 Automatic Acoustic Management (AAM) feature set <br> 4.14 48-bit Address feature set<br> 4.15 Device Configuration Overlay feature set <br> 4.16 Media Card Pass Through Command feature set<br> 4.17 Streaming feature set <br> 4.18 General Purpose Logging feature set <br> 4.19 Overlapped feature set <br> 4.20 Queued feature set<br> 4.21 Long physical sector feature set for non-packet devices<br> 4.22 Long logical Sector feature set for non-packet devices <br> 4.23 Devices implementing the Long Physical Sector Feature <br> Set and the Long Logical Feature Sector Set <br>5 I/O register descriptions<br> 5.1 Overview<br> 5.2 Alternate Status register<br> 5.3 Command register<br> 5.4 Data port<br> 5.5 Data register<br> 5.6 Device register <br> 5.7 Device control register <br> 5.8 Error register<br> 5.9 Features register<br> 5.10 LBA High/Byte Count High register<br> 5.11 LBA Low register<br> 5.12 LBA Mid/Byte Count Low register <br> 5.13 Sector Count/Interrupt Reason register<br> 5.14 Status register<br> 5.15 Signature and persistence<br> 5.16 Single device configurations<br>6 Command descriptions<br> 6.1 Overview<br> 6.2 CFA ERASE SECTORS<br> 6.3 CFA REQUEST EXTENDED ERROR CODE<br> 6.4 CFA TRANSLATE SECTOR <br> 6.5 CFA WRITE MULTIPLE WITHOUT ERASE<br> 6.6 CFA WRITE SECTORS WITHOUT ERASE<br> 6.7 CHECK MEDIA CARD TYPE<br> 6.8 CHECK POWER MODE<br> 6.9 CONFIGURE STREAM<br> 6.10 DEVICE CONFIGURATION<br> 6.11 DEVICE RESET <br> 6.12 DOWNLOAD MICROCODE<br> 6.13 EXECUTE DEVICE DIAGNOSTIC<br> 6.14 FLUSH CACHE<br> 6.15 FLUSH CACHE EXT<br> 6.16 GET MEDIA STATUS <br> 6.17 IDENTIFY DEVICE<br> 6.18 IDENTIFY PACKET DEVICE<br> 6.19 IDLE<br> 6.20 IDLE IMMEDIATE<br> 6.21 MEDIA EJECT<br> 6.22 MEDIA LOCK <br> 6.23 MEDIA UNLOCK<br> 6.24 NOP<br> 6.25 PACKET<br> 6.26 READ BUFFER<br> 6.27 READ DMA<br> 6.28 READ DMA EXT<br> 6.29 READ DMA QUEUED<br> 6.30 READ DMA QUEUED EXT <br> 6.31 READ LOG EXT <br> 6.32 READ MULTIPLE <br> 6.33 READ MULTIPLE EXT<br> 6.34 READ NATIVE MAX ADDRESS<br> 6.35 READ NATIVE MAX ADDRESS EXT<br> 6.36 READ SECTOR(S) <br> 6.37 READ SECTOR(S) EXT <br> 6.38 READ STREAM DMA EXT<br> 6.39 READ STREAM EXT<br> 6.40 READ VERIFY SECTOR(S)<br> 6.41 READ VERIFY SECTOR(S) EXT<br> 6.42 SECURITY DISABLE PASSWORD<br> 6.43 SECURITY ERASE PREPARE <br> 6.44 SECURITY ERASE UNIT<br> 6.45 SECURITY FREEZE LOCK<br> 6.46 SECURITY SET PASSWORD<br> 6.47 SECURITY UNLOCK<br> 6.48 SERVICE <br> 6.49 SET FEATURES<br> 6.50 SET MAX <br> 6.51 SET MAX ADDRESS EXT<br> 6.52 SET MULTIPLE MODE<br> 6.53 SLEEP <br> 6.54 SMART<br> 6.55 STANDBY<br> 6.56 STANDBY IMMEDIATE<br> 6.57 WRITE BUFFER<br> 6.58 WRITE DMA<br> 6.59 WRITE DMA EXT <br> 6.60 WRITE DMA FUA EXT <br> 6.61 WRITE DMA QUEUED <br> 6.62 WRITE DMA QUEUED EXT<br> 6.63 WRITE DMA QUEUED FUA EXT<br> 6.64 WRITE LOG EXT<br> 6.65 WRITE MULTIPLE<br> 6.66 WRITE MULTIPLE EXT<br> 6.67 WRITE MULTIPLE FUA EXT<br> 6.68 WRITE SECTOR(S)<br> 6.69 WRITE SECTOR(S) EXT<br> 6.70 WRITE STREAM DMA EXT<br> 6.71 WRITE STREAM EXT<br>7 Parallel interface physical and electrical requirements <br>8 Parallel interface signal assignments and descriptions <br>9 Parallel interface general operating requirements of the <br> physical, data link, and transport layers <br>10 Parallel interface register addressing <br>11 Parallel interface transport Protocols <br>12 Parallel interface timing <br>13 Serial interface overview <br>14 Serial interface physical layer <br>15 Serial interface link layer <br>16 Serial interface transport layer <br>17 Serial interface device command layer <br>18 Host command layer <br>19 Serial interface host adapter register interface <br>20 Serial interface error handling <br>Annex A (informative) - Command Set summary <br>Annex B (informative) - Design and programming considerations <br> for large physical sector devices<br>Annex C - Device determination of cable type (informative) <br>Annex D - Signal integrity and UDMA guide (informative) <br>Annex E - Register selection address summary (informative) <br>Annex F - Sample code for CRC and scrambling (informative) <br>Annex G - FIS type field value selection (informative) <br>Annex H - Physical layer implementation examples (informative) <br>Annex I - Command processing Example (informative) <br>Bibliography
Describes the AT Attachment Interface between host systems and storage devices. It also provides a common attachment interface for systems manufacturers, system integrators, software suppliers and suppliers of intelligent storage devices.
Published | |
Document Type | Standard |
Status | Current |
Publisher | International Organization for Standardization |
Pages | |
ISBN | |
Committee | JTC 1 |